Post Layout Optimization Methods for Structured ASIC

Authors

  • T. Tulbure Transilvania University of Brasov, Romania
  • R. Jipa Transilvania University of Brasov, Romania

Keywords:

timing optimization, layout, digital integrated circuits, structured ASIC

Abstract

The paper presents new methodologies for the post-layout optimization method dedicated to Structured ASIC. The target is meeting timing with small modifications on preexisting layout data. Several techniques are described emphasizing a new ECO type optimization method.

Author Biographies

T. Tulbure, Transilvania University of Brasov, Romania

Dept. of Electronics and Computers

R. Jipa, Transilvania University of Brasov, Romania

Dept. of Electronics and Computers

Published

2008-12-17

Issue

Vol. 1(50)(2008)

Section

ELECTRICAL ENGINEERING, ELECTRONICS AND AUTOMATICS