Specman-UVM Based Testbench

Abstract

The scope of the document is to present the advantages of using the Universal Verification Methodology (UVM) in creating a verification environment for a given block of the chip over others methodologies. The Hardware Verification Language (HVL) in which the testbench is written is called Specman. The paper will cover the basic building blocks of a Universal Verification Component (UVC) and the way they are used in creating a flexible testbench and validating a given Device Under Test (DUT).