Specman-E Testbench

Abstract

The scope of this document is to present a Verification Environment (VE) and how useful is the functional verification of a specific Device Under Test (DUT) in the process of developing and pouring into silicon a digital integrated circuit. The Hardware Verification Language (HVL) used for implementation is Specman. This paper will show the interconnection of the DUT with our VE, coverage results, and the bugs found. Also, it will point out that verifying the integrated circuit in an early stage will bring savings to the project even though the release date of the chip is delayed.