Synchronous Hardware Realization of Time-Delayed Petri Nets

Abstract

The paper presents a synchronous hardware realization of a control technique interpreted Petri net (SIN) model for a sequential machine. The switching behavior is reflected in the delayed Petri net as a maximum step switching strategy, by the fact that the enabled transitions are fired in parallel and also simultaneously to the positive edge of a clock pulse. The modeling and implementation of the sequential machine, as an example of the application of the proposed method, will be shown.